The idea of incorporating monitoring circuitry into product integrated circuits (ICs) is gaining relevance/momentum. A driving force behind this is that, as line widths decrease, IC performance errors become more frequent due to parasitic effects such as crosstalk, noise, etc. Although such monitoring circuitry requires some area on the IC and extra power, such drawbacks are greatly offset by the ability to monitor various IC parameters and address errors.
Accordingly, signal-integrity measurement systems are used in electronic circuitry, e.g., system-on-chip (SoC) circuits, and allow real-time monitoring of parameters that characterize the electrical behavior of the integrated circuit. These parameters give an indication of the circuit's robustness and performance during testing, debugging, or in operational use. Examples of such signal-integrity measurement systems are discussed in, e.g., US 20080007246, US 20070079188 and WO2006056951, all incorporated herein by reference.
FIG. 1 is a block diagram of a CMOS chip 100 with a signal-integrity self-test (SIST) configuration. Chip 100 comprises functional blocks 102, 104 and 106. Each of blocks 102-106 performs a respective function appropriate to the operation of chip 100. Operation of blocks 102-106 is monitored by monitors 108, 110 and 112, respectively. Monitors 108-112 are connected through a bus to a SIST controller 114. Different types of monitors are used to measure different phenomena: cross talk, supply noise, substrate noise, temperature, switching activity, clock duty-cycle, technology parameters etc. Preferably, each of monitors 108-112 fits into the standard-cell library design style and affects the total design as little as possible. Monitors 108-112 preferably use the local power supply (not shown), generate their own reference values and can be fully switched off. All analog sensing and processing as well as the conversion into a digital format are done locally at the respective monitor. The outputs of monitors 108-112 are digital signals, which are transferred to SIST processor 114. Controller 114 has an external interface 116, e.g., based on the IEEE Standard Test Access Port and Boundary-Scan Architecture, described in IEEE Std 1149.1-1990. Further details of the SIST configuration are disclosed in WO2006056951, mentioned above and in “A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs”, Violeta Petrescu, Marcel Pelgrom Harry Veendrick, Praveen Pavithran, Jean Wieling, ISSCC Feb. 8, 2006, session 29.6, and in “Monitors for a signal integrity system”, ESSCIRC 2006, Montreux, pp. 122-125 by the same authors.
Examples of parameters that can be monitored in above approach are temperature, voltage and current.